Ok, coming back to compiling, you will see that the simulator does print anything on screen, or dump any waveform. Of course it is a very good idea to keep file names the same as the module name. You need to give command line options as shown below. All the above depends on the specs of the DUT and the creativity of a 'Test Bench Designer'.Īt this point, you would like to test if the testbench is generating the clock correctly: well you can compile it with any Verilog simulator. You may write a complex clock generator, where we could introduce PPM (Parts per million, clock width drift), then control the duty cycle.

You could a add parameter or use `define to control the clock frequency. There are many ways to generate a clock: one could use a forever loop inside an initial block as an alternative to the above code. Before we add a clock generator we need to drive all the inputs to DUT to some known state as shown in the code below.Ģ1 22 endmodule You could download file counter_tb2.v hereĪn initial block in Verilog is executed only once, thus simulator sets the value of clk, reset and enable to 0 by looking at the counter code (of course you will be referring to the DUT specs) could be found that driving 0 makes all these signals disabled. Next step would be to add clock generator logic: this is straight forward, as we know how to generate a clock. Note that there is no port list for the test bench.ġ1 12 endmodule You could download file counter_tb1.v here First step of any testbench creation is building a dummy template which basically declares inputs to DUT as reg and outputs from DUT as wire, then instantiates the DUT as shown in the code below.

Verilog testbench clock